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preliminary 9-mbit (256k x 36/512k x 18) pipelined sram cy7c1360c cy7c1362c cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05540 rev. *c revised february 23, 2005 features ? supports bus operation up to 250 mhz ? available speed grades are 250, 200, and 166 mhz ? registered inputs and outputs for pipelined operation ? 3.3v core power supply ? 2.5v/3.3v i/o operation ? fast clock-to-output times ? 2.8 ns (for 250-mhz device) ? 3.0 ns (for 200-mhz device) ? 3.5 ns (for 166-mhz device) ? provide high-performance 3-1-1-1 access rate ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed writes ? asynchronous output enable ? single cycle chip deselect ? offered in lead-free 100-pin tqfp, 119-ball bga and 165-ball fbga packages ? tqfp available with 3-chip enable and 2-chip enable ? ieee 1149.1 jtag-compatible boundary scan ? ?zz? sleep mode option functional description [1] the cy7c1360c/cy7c1362c sram integrates 262,144 x 36 and 524,288 x 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 [2] ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write co ntrols are registered on-chip to initiate a self-timed write cycl e.this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. gw when active low cause s all bytes to be written. the cy7c1360c/cy7c1362c operates from a +3.3v core power supply while all outputs may operate with either a +2.5 or +3.3v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. notes: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. 2. ce 3 is for a version of tqfp (3 chip enable option) and 165 fbga package only. 119 bga is offered only in 2 chip enable. address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a 0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register dq d , dqp d byte write register dq a , dqp a byte write driver dq b , dqp b byte write driver dq c , dqp c byte write driver dq d ,dqp d byte write driver logic block diagram ? cy7c1360c (256k x 36)
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 2 of 31 selection guide 250 mhz 200 mhz 166 mhz unit maximum access time 2.8 3.0 3.5 ns maximum operating current 250 220 180 ma maximum cmos standby current 30 30 30 ma shaded areas contain advance information. plea se contact your local cypress sales repr esentative for availability of these part s. a 0, a1, a address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b write register dq a, dqp a write register enable register oe sense amps memory array adsp 2 mode ce2 ce3 gw bwe pipelined enable dqs dqp a dqp b output registers input registers e dq a, dqp a write driver output buffers dq b, dqp b write driver a[1:0] zz sleep control logic block diagram ? cy7c1362c (512k x 18)
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 3 of 31 pin configurations a a a a a 1 a 0 nc / 72m nc / 36m v ss v dd nc / 18m a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dqc v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1360c (256k x 36) nc a a a a a 1 a 0 nc / 72m nc / 36m v ss v dd nc / 18m a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1362c (512k x 18) nc 100-pin tqfp pinout (3 chip enables) (a version)
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 4 of 31 pin configurations (continued) a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a a v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1360c (256k x 36) nc a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a a v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1362c (512k x 18) nc 100-pin tqfp (2 chip enables) (aj version) nc nc
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 5 of 31 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u v ddq nc/288m nc/144m dqp c dq c dq d dq c dq d aa aa adsp v ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/576m nc/1g nc nc tdo tck tdi tms nc/36m nc/72m nc v ddq v ddq v ddq aaa a a a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc bwe bw d zz 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc/288m nc/144m nc dq b dq b dq b dq b aa aa adsp v ddq ce 2 a nc v ddq nc v ddq v ddq v ddq nc nc nc nc/72m v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/576m nc/1g nc nc tdo tck tdi tms a a nc v ddq v ddq v ddq a nc/36m a a a a a a a a a a0 a1 dq a dq b nc nc dq a nc dq a dq a nc nc dq a nc dq a nc dq a nc dq a v dd nc dq b nc v dd dq b nc dq b nc adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss nc mode dqp b dqp a v ss bw b nc v dd nc bw a nc bwe v ss zz cy7c1362c (512k x 18) cy7c1360c (256k x 36) 119-ball bga (2 chip enables with jtag)
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 6 of 31 pin configurations (continued) 165-ball fbga (3 chip enable with jtag) cy7c1360c (256k x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc / 36m nc / 72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc / 18m v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c v ss v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc / 576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a cy7c1362c (512k x 18) a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc/144m nc nc dqp b nc dq b a ce 1 nc ce 3 bw b bwe a ce2 nc dq b dq b mode nc dq b dq b nc nc nc nc / 36m nc / 72m v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc / 18m v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc v ss v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc / 576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 7 of 31 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 [2] are sampled active. a 1 , a 0 are fed to the two-bit counter. . bw a , bw b bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 [2] to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 [2] to select/desel ect the device. ce 2 is sampled only when a new external address is loaded. ce 3 [2] input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. not available for aj package version. not connected for bga. where referenced, ce 3 [2] is assumed active throughout this document for bga. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the firs t clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically increm ents the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a 1 , a 0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a 1 , a 0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data in tegrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs, dqp x i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as out puts, they deliver the data contained in the memory location specified by the addresses pres ented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a three-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ssq i/o ground ground for the i/o circuitry . v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst seq uence. this is a strap pin and should remain static during device operation. m ode pin has an internal pull-up. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utilized, this pin should be disconnected. this pin is not available on tqfp packages.
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 8 of 31 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 2.8 ns (250-mhz device). the cy7c1360c/cy7c1362c supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with ei ther the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the firs t address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 [2] ) and an asynchronous output enable (oe ) provide for easy bank selection and output thr ee-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at cloc k rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 [2] are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address advancement logic and the address register while being presented to the memory array. the corresponding data is allowed to propagate to the input of the output registers. at the risi ng edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.8 ns (250-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutiv e single read cycles are supported. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will three-state immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at cl ock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 [2] are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses require two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dqs inputs is written into the corre- sponding address location in the memory array. if gw is high, then the write operation is controlled by bwe and bw x signals. the cy7c1360c/cy7c1362c provides byte write capability that is described in the write cycle descriptions table. asserting the byte write enable input (bwe ) with the selected byte write (bw x ) input, will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1360c/cy7c1362c is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so will three-state the output drivers. as a safety precaution, dqs are automatically three-stated whenev er a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) ce 1 , ce 2 , ce 3 [2] are all asserted active, and (4) the appropriate combinat ion of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs is written into the corresponding address location in the memory core. if a byte write is conducted, only the se lected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pi n can be disconnected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pi n can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to th e jtag circuitry . if the jtag featur e is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die pin definitions (continued) name i/o description
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 9 of 31 because the cy7c1360c/cy7c1362c is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so will three-state the output drivers. as a safety precaution, dqs are automatically three-stated whenever a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1360c/cy7c1362c provides a two-bit wraparound counter, fed by a 1 , a 0 , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to suppo rt intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 [2] , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a 1 , a 0 second address a 1 , a 0 third address a 1 , a 0 fourth address a 1 , a 0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a 1 , a 0 second address a 1 , a 0 third address a 1 , a 0 fourth address a 1 , a 0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 50 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current this parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns truth table [3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power down none h x x l x l x x x l-h three-state deselect cycle, power down none l l x l l x x x x l-h three-state deselect cycle, power down none l x h l l x x x x l-h three-state deselect cycle, power down none l l x l h l x x x l-h three-state deselect cycle, power down none l x h l h l x x x l-h three-state sleep mode, power down none x x x h x x x x x x three-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h three-state notes: 3. x = ?don't care.? h = logic high, l = logic low. 4. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 5. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. ce 1 , ce 2 , and ce 3 are available only in the tqfp package. bga package has only two chip selects ce 1 and ce 2 . 7. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the out puts to three-state. oe is a don't care for the remainder of the write cycle 8. oe is asynchronous and is not sampled with t he clock rise. it is masked internally dur ing write cycles. during a read cycle all d ata bits are three-state when oe is inactive or when the device is deselect ed, and all data bits behave as output when oe is active (low) .
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 10 of 31 write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h three-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h three-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h three-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h three-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h three-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d partial truth table for read/write [5, 9] function (cy7c1360c) gw bwe bw d bw c bw b bw a read hhxxxx read hlhhhh write byte a ? (dq a and dqp a ) hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c ) hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d ) hl lhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b hllllh write all bytes hlllll write all bytes lxxxxx note: 9. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active. truth table (continued) [3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 11 of 31 ieee 1149.1 serial boundary scan (jtag) the cy7c1360c/cy7c1362c incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this part operates in accordance with ieee standard 1149.1-1900, but doesn?t have the set of functions required for full 1149.1 compliance. these functions fr om the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 3. 3v or 2.5v i/o logic levels. the cy7c1360c/cy7c1362c contains a tap controller, instruction register, boundary sc an register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) truth table for read/write [5, 9] function (cy7c1362c) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write bytes b, a h l l l write all bytes h l l l write all bytes l x x x test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 tap controller state diagram
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 12 of 31 tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this rese t does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset in ternally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed betwe en the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the conten ts of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it per forms a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instructi on register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. un like the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 13 of 31 the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructi ons are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the captur e-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 14 of 31 3.3v tap ac test conditions input pulse levels ................................................ v ss to 3.3v input rise and fall times ........... .......... ..............................1 ns input timing reference levels ...........................................1.5v output reference levels...................................................1.5v test load termination supply voltage...............................1.5v 3.3v tap ac output load equivalent 2.5v tap ac test conditions input pulse levels ........................................... v ss to 2.5v input rise and fall time .....................................................1 ns input timing reference levels...... ............. ......................1.25v output reference levels ............. ..... ..............................1.25v test load termination supply voltage .................... ........1.25v 2.5v tap ac output load equivalent tap ac switching characteristics over the operating range [10, 11] parameter description min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 25 ns t tl tck clock low time 25 ns output times t tdov tck clock low to tdo valid 5 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns t do 1.5v 20p f z = 50 w o 50 w t do 1.25v 20p f z = 50 w o 50 w tap dc electrical characteristics and operating conditions (0c < ta < +70c; vdd = 3.3v 0.165v unless otherwise noted) [12] parameter description conditions min. max. unit v oh1 output high voltage i oh = ?4.0 ma v ddq = 3.3v 2.4 v i oh = ?1.0 ma v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 3.3v 2.9 v v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3v 0.4 v i ol = 8.0 ma v ddq = 2.5v 0.4 v notes: 10. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1ns.
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 15 of 31 v ol2 output low voltage i ol = 100 a v ddq = 3.3v 0.2 v v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3 v v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3v ?0.5 0.7 v v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a identification register definitions instruction field cy7c1360c (256kx36) cy7c1362c (512kx18) description revision number (31:29) 000 000 describes the version number device depth (28:24) [13] 01011 01011 reserved for internal use device width (23:18) 000000 000000 defines memory type and architecture cypress device id (17:12) 100110 010110 defines width and density cypress jedec id code (11:1) 00000110100 000001 10100 allows unique identification of sram vendor id register presence indicator (0) 1 1 i ndicates the presence of an id register tap dc electrical characteristics and operating conditions (0c < ta < +70c; vdd = 3.3v 0. 165v unless otherwise noted) (continued) [12] parameter description conditions min. max. unit scan register sizes register name bit size (x36) bit size (x18) instruction 3 3 bypass 1 1 id 32 32 boundary scan order (119-ball bga package) 71 71 boundary scan order (165-ball fbga package) 71 71 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. plac es the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. pl aces the boundary scan regi ster between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. notes: 12. all voltages referenced to v ss (gnd). 13. bit #24 is ?1? in the register definitions fo r both 2.5v and 3.3v ve rsions of this device.
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 16 of 31 ac test loads and waveforms [14] note: 14. tested initially and after any design or process change that may affect these parameters. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 3.3v i/o test load 2.5v i/o test load
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 17 of 31 165-ball fbga boundary scan order cy7c1360c (256k x 36) cy7c1362c (512k x 18) bit# ball id signal name bit# ball id signal name bit# ball id signal name bit# ball id signal name 1 b6 clk 37 r6 a0 1 b6 clk 37 r6 a0 2b7gw 38 p6 a1 2 b7 gw 38 p6 a1 3a7bwe 39 r4 a 3 a7 bwe 39 r4 a 4b8oe 40 p4 a 4 b8 oe 40 p4 a 5a8adsc 41 r3 a 5 a8 adsc 41 r3 a 6b9adsp 42 p3 a 6 b9 adsp 42 p3 a 7a9adv 43 r1 mode 7 a9 adv 43 r1 mode 8b10 a 44 n1 dqp d 8 b10 a 44 internal internal 9a10 a 45 l2 dq d 9 a10 a 45 internal internal 10 c11 dqp b 46 k2 dq d 10 a11 a 46 internal internal 11 e10 dq b 47 j2 dq d 11 internal internal 47 internal internal 12 f10 dq b 48 m2 dq d 12 internal internal 48 n1 dqp b 13 g10 dq b 49 m1 dq d 13 internal internal 49 m1 dq b 14 d10 dq b 50 l1 dq d 14 c11 dqp a 50 l1 dq b 15 d11 dq b 51 k1 dq d 15 d11 dq a 51 k1 dq b 16 e11 dq b 52 j1 dq d 16 e11 dq a 52 j1 dq b 17 f11 dq b 53 internal internal 17 f11 dq a 53 internal internal 18 g11 dq b 54 g2 dq c 18 g11 dq a 54 g2 dq b 19 h11 zz 55 f2 dq c 19 h11 zz 55 f2 dq b 20 j10 dq a 56 e2 dq c 20 j10 dq a 56 e2 dq b 21 k10 dq a 57 d2 dq c 21 k10 dq a 57 d2 dq b 22 l10 dq a 58 g1 dq c 22 l10 dq a 58 internal internal 23 m10 dq a 59 f1 dq c 23 m10 dq a 59 internal internal 24 j11 dq a 60 e1 dq c 24 internal internal 60 internal internal 25 k11 dq a 61 d1 dq c 25 internal internal 61 internal internal 26 l11 dq a 62 c1 dqp c 26 internal internal 62 internal internal 27 m11 dq a 63 b2 a 27 internal internal 63 b2 a 28 n11 dqp a 64 a2 a 28 internal internal 64 a2 a 29 r11 a 65 a3 ce 1 29 r11 a 65 a3 ce 1 30 r10 a 66 b3 ce 2 30 r10 a 66 b3 ce 2 31 p10 a 67 b4 bw d 31 p10 a 67 internal internal 32 r9 a 68 a4 bw c 32 r9 a 68 internal internal 33 p9 a 69 a5 bw b 33 p9 a 69 a4 bw b 34 r8 a 70 b5 bw a 34 r8 a 70 b5 bw a 35 p8 a 71 a6 ce 3 35 p8 a 71 a6 ce 3 36 p11 a 36 p11 a
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 18 of 31 119-ball bga boundary scan order cy7c1360c (256k x 36) cy7c1362c (512k x 18) bit# ball id signal name bit# ball id signal name bit# ball id signal name bit# ball id signal name 1 k4 clk 37 p4 a0 1 k4 clk 37 p4 a0 2h4 gw 38 n4 a1 2 h4 gw 38 n4 a1 3m4bwe 39 r6 a 3 m4 bwe 39 r6 a 4f4 oe 40 t5 a 4 f4 oe 40 t5 a 5b4adsc 41 t3 a 5 b4 adsc 41 t3 a 6a4adsp 42 r2 a 6 a4 adsp 42 r2 a 7g4adv 43 r3 mode 7 g4 adv 43 r3 mode 8c3 a 44 p2 dqp d 8 c3 a 44 internal internal 9b3 a 45 p1 dq d 9 b3 a 45 internal internal 10 d6 dqp b 46 l2 dq d 10 t2 a 46 internal internal 11 h7 dq b 47 k1 dq d 11 internal internal 47 internal internal 12 g6 dq b 48 n2 dq d 12 internal internal 48 p2 dqp b 13 e6 dq b 49 n1 dq d 13 internal internal 49 n1 dq b 14 d7 dq b 50 m2 dq d 14 d6 dqp a 50 m2 dq b 15 e7 dq b 51 l1 dq d 15 e7 dq a 51 l1 dq b 16 f6 dq b 52 k2 dq d 16 f6 dq a 52 k2 dq b 17 g7 dq b 53 internal internal 17 g7 dq a 53 internal internal 18 h6 dq b 54 h1 dq c 18 h6 dq a 54 h1 dq b 19 t7 zz 55 g2 dq c 19 t7 zz 55 g2 dq b 20 k7 dq a 56 e2 dq c 20 k7 dq a 56 e2 dq b 21 l6 dq a 57 d1 dq c 21 l6 dq a 57 d1 dq b 22 n6 dq a 58 h2 dq c 22 n6 dq a 58 internal internal 23 p7 dq a 59 g1 dq c 23 p7 dq a 59 internal internal 24 n7 dq a 60 f2 dq c 24 internal internal 60 internal internal 25 m6 dq a 61 e1 dq c 25 internal internal 61 internal internal 26 l7 dq a 62 d2 dqp c 26 internal internal 62 internal internal 27 k6 dq a 63 c2 a 27 internal internal 63 c2 a 28 p6 dqp a 64 a2 a 28 internal internal 64 a2 a 29 t4 a 65 e4 ce 1 29 t6 a 65 e4 ce 1 30 a3 a 66 b2 ce 2 30 a3 a 66 b2 ce 2 31 c5 a 67 l3 bw d 31 c5 a 67 internal internal 32 b5 a 68 g3 bw c 32 b5 a 68 internal internal 33 a5 a 69 g5 bw b 33 a5 a 69 g3 bw b 34 c6 a 70 l5 bw a 34 c6 a 70 l5 bw a 35 a6 a 71 internal internal 35 a6 a 71 internal internal 36 b6 a 36 b6 a
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 19 of 31 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on vdd relative to gnd ...... ?0.5v to +4.6v dc voltage applied to outputs in three-state ....................... .............?0.5v to vddq + 0.5v dc input voltage...................................?0.5v to vdd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ? 5%/+10% 2.5v ? 5% to v dd industrial ?40c to +85c electrical characteristics over the operating range [15, 16] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage v ddq = 3.3v 3.135 v dd v v ddq = 2.5v 2.375 2.625 v v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ?4.0 ma 2.4 v v ddq = 2.5v, v dd = min., i oh = ?1.0 ma 2.0 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ddq = 2.5v, v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage [15] v ddq = 3.3v 2.0 v dd + 0.3v v v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [15] v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 250 ma 5-ns cycle, 200 mhz 220 ma 6-ns cycle, 166 mhz 180 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 130 ma 5-ns cycle, 200 mhz 120 ma 6-ns cycle, 166 mhz 110 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 30 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 120 ma 5-ns cycle, 200 mhz 110 ma 6-ns cycle, 166 mhz 100 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = 0 all speeds 40 ma shaded areas contain advance information. notes: 15. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 16. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd .
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 20 of 31 thermal resistance [14] parameter description test conditions 100 tqfp package 119 bga package 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 29.41 34.1 16.8 c/w jc thermal resistance (junction to case) 6.13 14.0 3 c/w capacitance [14] parameter description test conditions 100 tqfp package 119 bga package 165 fbga package unit c in input capacitance t a = 25c, f = 1 mhz, v dd = 3.3v v ddq = 2.5v 555pf c clk clock input capacitance 5 5 5 pf c i/o input/output capacitance 5 7 7 pf ac test loads and waveforms switching characteristics over the operating range [17, 18] parameter description 250 mhz 200 mhz 166 mhz unit min. max min. max min. max t power v dd (typical) to the first access [19] 1 1 1 ms clock t cyc clock cycle time 4.0 5.0 6.0 ns t ch clock high 1.8 2.0 2.4 ns t cl clock low 1.8 2.0 2.4 ns output times t co data output valid after clk rise 2.8 3.0 3.5 ns t doh data output hold after clk rise 1.25 1.25 1.25 ns notes: 17. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 18. test conditions shown in (a) of ac test loads unless otherwise noted. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 3.3v i/o test load 2.5v i/o test load
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 21 of 31 t clz clock to low-z [20, 21, 22] 1.25 1.25 1.25 ns t chz clock to high-z [20, 21, 22] 1.25 2.8 1.25 3.0 1.25 3.5 ns t oev oe low to output valid 2.8 3.0 3.5 ns t oelz oe low to output low-z [20, 21, 22] 0 0 0 ns t oehz oe high to output high-z [20, 21, 22] 2.8 3.0 3.5 ns set-up times t as address set-up before clk rise 1.4 1.5 1.5 ns t ads adsc , adsp set-up before clk rise 1.4 1.5 1.5 ns t advs adv set-up before clk rise 1.4 1.5 1.5 ns t wes gw , bwe , bw x set-up before clk rise 1.4 1.5 1.5 ns t ds data input set-up before clk rise 1.4 1.5 1.5 ns t ces chip enable set-up before clk rise 1.4 1.5 1.5 ns hold times t ah address hold after clk rise 0.4 0.5 0.5 ns t adh adsp , adsc hold after clk rise 0.4 0.5 0.5 ns t advh adv hold after clk rise 0.4 0.5 0.5 ns t weh gw , bwe , bw x hold after clk rise 0.4 0.5 0.5 ns t dh data input hold after clk rise 0.4 0.5 0.5 ns t ceh chip enable hold after clk rise 0.4 0.5 0.5 ns shaded areas contain advance information. notes: 19. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially before a read or write operation can be initiated. 20. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 21. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention co ndition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 22. this parameter is sampled and not 100% tested. switching characteristics over the operatin g range (continued) [17, 18] parameter description 250 mhz 200 mhz 166 mhz unit min. max min. max min. max
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 22 of 31 switching waveforms read cycle timing [23] note: 23. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bwx d ata out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address don?t care undefined
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 23 of 31 write cycle timing [23, 24] note: 24. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x d ata out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 24 of 31 read/write cycle timing [23, 25, 26] notes: 25. the data bus (q) remains in high-z following a writ e cycle, unless a new read access is initiated by adsp or adsc . 26. gw is high. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw x d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 don?t care undefined a3
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 25 of 31 zz mode timing [27, 28] ordering information speed (mhz) ordering code package name part and package type operating range 250 cy7c1360c-250axc cy7c1362c-250axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1360c-250axi cy7c1362c-250axi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables industrial cy7c1360c-250ajxc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 2 chip enables commercial cy7c1362c-250ajxc cy7c1360c-250ajxi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 2 chip enables industrial cy7c1362c-250ajxi cy7c1360c-250bgc bg119 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag commercial cy7c1362c-250bgc cy7c1360c-250bgi bg119 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag industrial cy7c1362c-250bgi cy7c1360c-250bzc bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag commercial cy7c1362c-250bzc cy7c1360c-250bzi bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag industrial cy7c1362c-250bzi cy7c1360c-250bgxc bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag commercial cy7c1362c-250bgxc cy7c1360c-250bgxi bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag industrial cy7c1362c-250bgxi cy7c1360c-250bzxc bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag commercial cy7c1362c-250bzxc cy7c1360c-250bzxi bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag industrial cy7c1362c-250bzxi notes: 27. device must be deselected when entering zz mode. see cycle desc riptions table for all possible signal conditions to deselect the device. 28. dqs are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 26 of 31 200 cy7c1360c-200axc cy7c1362c-200axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1360c-200axi cy7c1362c-200axi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables industrial cy7c1360c-200ajxc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 2 chip enables commercial cy7c1362c-200ajxc cy7c1360c-200ajxi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 2 chip enables industrial cy7c1362c-200ajxi cy7c1360c-200bgc bg119 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag commercial cy7c1362c-200bgc cy7c1360c-200bgi bg119 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag industrial cy7c1362c-200bgi cy7c1360c-200bzc bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag commercial cy7c1362c-200bzc cy7c1360c-200bzi bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag industrial cy7c1362c-200bzi cy7c1360c-200bgxc bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag commercial cy7c1362c-200bgxc cy7c1360c-200bgxi bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag industrial cy7c1362c-200bgxi cy7c1360c-200bzxc bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag commercial cy7c1362c-200bzxc cy7c1360c-200bzxi bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag industrial cy7c1362c-200bzxi ordering information (continued) speed (mhz) ordering code package name part and package type operating range
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 27 of 31 166 CY7C1360C-166AXC a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1362c-166axc cy7c1360c-166axi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables industrial cy7c1362c-166axi cy7c1360c-166ajxc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 2 chip enables commercial cy7c1362c-166ajxc cy7c1360c-166ajxi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 2 chip enables industrial cy7c1362c-166ajxi cy7c1360c-166bgc bg119 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag commercial cy7c1362c-166bgc cy7c1360c-166bgi bg119 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag industrial icy7c1362c-166bgi cy7c1360c-166bzc bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag commercial cy7c1362c-166bzc cy7c1360c-166bzi bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag industrial icy7c1362c-166bzi cy7c1360c-166bgxc bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag commercial cy7c1362c-166bgxc cy7c1360c-166bgxi bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 2 chip enables and jtag industrial icy7c1362c-166bgxi cy7c1360c-166bzxc bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag commercial cy7c1362c-166bzxc cy7c1360c-166bzxi bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag industrial cy7c1362c-166bzxi shaded areas contain advance information. plea se contact your local sales representative for availability of these parts. ordering information (continued) speed (mhz) ordering code package name part and package type operating range
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 28 of 31 package diagrams dimensions are in millimeters. 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 29 of 31 package diagrams (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 30 of 31 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. i486 is a trademark, and intel and pentium are registered tr ademarks of intel corporation. powerpc is a trademark of ibm corporation. all product and company names mentioned in th is document are the trademarks of their respective holders. package diagrams (continued) 51-85180-** 165 fbga 13 x 15 x 1.40 mm bb165d
preliminary cy7c1360c cy7c1362c document #: 38-05540 rev. *c page 31 of 31 document history page document title: cy7c1360c/cy7c1362c 9-mbit (256k x 36/512k x 18) pipelined sram document number: 38-05540 rev. ecn no. issue date orig. of change description of change ** 241690 see ecn rkf new data sheet *a 278130 see ecn rkf changed boundary scan order to match the b rev of these devices. changed tqfp pkg to lead-free tqfp in ordering information section added comment of lead-free bg and bz packages availability *b 248929 see ecn vbl changed isb1 and isb3 from dc characteristics table as follows: isb1: 225 mhz -> 130 ma, 200 mh z -> 120 ma, 167 mhz -> 110 ma isb3: 225 mhz -> 120 ma, 200 mhz -> 110 ma, 167 mhz -> 100 ma changed iddzz to 50ma. added bg and bz pkg lead-free part numbers to ordering info section. *c 323636 see ecn pci changed frequency of 225 mhz into 250 mhz added t cyc of 4.0 ns for 250 mhz changed ja and jc for tqfp package from 25 and 9 c/w to 29.41 and 6.13 c/w respectively changed ja and jc for bga package from 25 and 6 c/w to 34.1 and 14.0 c/w respectively changed ja and jc for fbga package from 27 and 6 c/w to 16.8 and 3.0 c/w respectively modified address expansion as per jedec standard removed comment of lead-free bg and bz packages availability

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